1. Field of the Invention
This invention relates generally to embedded circuits such as DRAM, and more specifically, a system and method for preventing noise cross-contamination between embedded DRAM and system chip.
2. Discussion of the Prior Art
Substrate noise caused by high speed digital circuits has been known as a key problem to the analog circuits on the mixed-signal system-on-chip designs. One major source of noise is from the clock generators of digital circuits. Unfortunately, in system-on-chip circuits comprising embedded DRAM, many free running oscillators are used to generate different internal power supply voltage levels. That is, noise generated from the DRAM macro is mainly from its DC generator block and the sense amplifier banks. Inside the generator block, DRAM macro contains several DC generators, including substrate bias (the Vbb) generator, the boost wordline (the Vpp generator, the negative wordline low (the Vwl) generator, etc. Each of the generators requires an oscillator to be used from the charge pump to generate a higher voltage level higher than Vdd supply, or lower than ground. The frequency of these oscillators is ranged from 5 MHZ to 50 MHZ. These oscillators are formed by, for example, several stages of inverter formed in a ring structure. When an oscillator oscillates, charges are constantly injected into n-well and substrate causing ground and Vdd bouncing. Not only the ring oscillators, but also the pump drivers, and the pumps themselves are sources of noise. Additionally, during DRAM array sensing, on the order of thousands of sense amplifiers are switched simultaneously. That is, for each sensing activity, couple thousands of sense amplifiers are set at the same time, as a result, the Vdd and ground bounding in the sense amplifier regions.
Noise generated from free-running oscillators (e.g., comprising power supply noise) and switching sense amplifiers (switching noise) will interfere with the noise-sensitive core circuits. For example, it has been reported that noise is caused by Vdd and substrate bounding affects the performance of high-precision analog circuits. For example, phase-locked loops used in communication circuits are sensitive to noise-induced clock jitters. To isolate the eDRAM from the noisy environment is very important.
U.S. Pat. No. 5,999,440 describes a system for enhancing noise immunity of an embedded DRAM in a System-on-Chip (SOC). In U.S. Pat. No. 5,999,440 there is described a noise immunity enhancing system for a pMOS eDRAM array. As well known in the industry a pMOS device has poorer performance than the nMOS counterpart under the same technology and ground rule because, electron mobility is inherently faster than hole mobility. DRAM using pMOS devices as the transfer gate is not the technology of choice. That is, almost 99% DRAM produced today all use nMOS to take advantage of the speed, so that the access time and cycle time can be fast. However, using pMOS device one can build pMOS array inside a n-well of a p type substrate which is naturally isolated from other circuits that are built in different n-wells. In this case, no triple-well is needed, therefore cost can be lower. Thus, U.S. Pat. No. 5,999,440 describes just a simple well process, with no teaching or suggestion to implement a triple well structure.
Besides a solution for optimizing the analog circuits to be more noise resistive, a simpler solution for eliminating the noise problem from these noisy circuits is to fabricate potentially noisy components in isolation such as by fabricating them in triple-well structures.
It is an object of the present invention to provide in mixed-signal circuits having analog and high-speed digital components which generate noise that interferes with the analog circuits, a system and method for eliminating the noise problem from these noisy circuits.
It is an object of the present invention to provide a more complete solution to block noise from an embedded DRAM (eDRAM) macro to an analog core, and vice verse, provided in an integrated circuit (IC).
Specifically, according to the principles of the invention, there is provided a structure to isolate oscillator, drivers, charge pumps, and sense amplifiers, so that noise is not able to propagate into the core or any noise sensitive area of the chip. For example, the noise from sense amplifier will not degrade the data integrity in the array, nor will it affect the quality of analog circuits in the core. First, a guard ring is built around the noisy device areas. Second, a triple well is applied to the same area to block the noise. Third, the ground and Vdd of the generators (from hereon called Vddc and Gndc) and those of the sense amplifiers (Vdds, and Gnds) are separated from those of the rest of the chip. Finally, each Vdd, i.e., Vdds and Vddc, will have its own decoupling capacitor assigned.
Advantageously, such a system and method is important for system-on chip designs comprising DRAM circuits embedded into analog circuits, for example, in the networking, RF, and wireless communications technological areas.